The present invention relates to a video signal processing device in an image display device (e.g., a crystal liquid display, or a plasma display) on which pixels are fixed in number for display and, more specifically, to a video signal processing device subjecting a video signal inputted into the image display device to A/D conversion with two-phase processing.
In recent years, with the advancement in resolution of a computer as an image signal source, a clock frequency for an image display device has been becoming increasingly faster. In order for the image display device to deal with the faster clock frequency, a digital signal processing device where an incoming A/D-converted video signal is processed is required to operate according to the faster clock. This brings about problems such as higher power consumption in the image display device, and an increase in cost, for example.
To get around such problems, a conventional image display device lowers the clock frequency to half by carrying out two-phase processing in an A/D converter. Thereby, the digital signal processing device provided in a stage subsequent to the A/D converter has no need to operate in accordance with the faster clock. Herein, the processing carried out in the A/D converter may be four-phase or six-phase, and is similarly effective to the two-phase processing.
Herein, as to the A/D converter carrying out the two-phase processing, various types of products are available. For example, these include a CXA3026AQ model (manufactured by SONY), and an AD9054BST model (manufactured by AnalogDevices).
FIG. 17 is a block diagram showing the structure of the conventional video signal processing device carrying out the two-phase processing in the A/D converter. In FIG. 17, the video signal processing device is an A/D converter 3 receiving a reference signal 9 and a video signal 24 from an image signal source, carrying out the two-phase processing, and outputting first phase data 10 and second phase data 11. Described next below is the operation of such video signal processing device with reference to FIGS. 17 and 18.
FIG. 18 is a diagram for explaining the operation of the A/D converter 3 in FIG. 17. In FIG. 18, a to e denote video data included in the video signal 24 in a valid video period. Blackened objects in the shape of a circle, diamond, square, and triangle denote data in the pedestal level, specifically black data, in a back porch. Moreover, t1 to t10 each indicate a certain time. Arrows therein schematically show the two-phase processing in the A/D converter 3.
In FIG. 18, the video signal 24 includes the back porch and the video data. The back porch is between time t1 (or before) and time t5, while the video signal data is included from time t5 and onward. Accordingly, the video signal 24 has such structure that a leading edge of a signal including the video data follows an end of the back porch.
Herein, with reference to a pulse of the reference signal 9 provided to the A/D converter 3, the digital data both outputted from the A/D converter 3 is determined based on a phase relationship between the digital data and the video signal 24. Generally, the reference signal 9 is a horizontal synchronizing signal provided from the image signal source.
First, as to the first phase data 10, with reference to the pulse of the reference signal 9, the A/D converter 3 starts the two-phase processing at time t1. As shown in FIG. 18, at time t3, the black data denoted by the blackened circle is outputted from the A/D Converter 3 as the first phase data 10. At the same time, the black data denoted by the diamond is outputted from the A/D converter 3 as the second phase data 11. Thereafter, similarly at time t5, the black data each denoted by the square and the triangle is outputted.
Accordingly, in the video signal 24, when the number of data in the back porch, that is from a leading edge of the pulse of the reference signal 9 to immediately before head data a, is even, the head data a is outputted from the A/D converter 3 as the first phase data 10. On the other hand, when the number of data in the back porch is odd, the head data a is outputted from the A/D converter 3 as the second phase data 11.
The problem herein is, if such conventional structure is applied, a display, e.g., a crystal liquid display or a plasma display, on which pixels are fixed in number for display, may be one dot short when displaying the video data. Next, such a problem is described below by referring to FIGS. 19 through 20(b).
FIG. 19 is a schematic diagram for explaining the arrangement of output data and display status on the display for a case where the video data a shown in FIG. 18 is outputted from the A/D converter as the first phase data. FIG. 20(a) is a schematic diagram for explaining the arrangement of output data and display status on the display for a case where the video data a shown in FIG. 18 is outputted from the A/D converter as the second phase data. FIG. 20(b) is a schematic diagram for explaining a case where the data arrangement is the same as in FIG. 20(a), but the display status is different therefrom.
In FIGS. 19 through 20(b), a to t denote data included in a video signal, from an image signal source, observed on an arbitrary scan line in a valid video period. Herein, the data inside of a frame in the shape of a square is displayed on the display, while the data outside of the frame is not displayed on the display.
As shown in FIG. 19, when the head data (data displayed on the left end on the display) a of the video signal is included in the first phase data 10 outputted from the A/D converter, the display where pixels displayed thereon are fixed in number displays every video data from a to t. On the other hand, as shown in FIGS. 20(a) and (b), when the head data a is included in the second phase data 11, either the video data t on the right end or the video data a on the left end is problematically not displayed on the display. This is because the digital signal processing device in the stage subsequent to the A/D converter 3 carries out processing in a frequency half of a dot clock coming from the image signal source, causing a video phase on the display to change only in pairs of pixels.
As is known from the above, with the conventional video signal processing device, when the head data a is included in the second phase data 11, the video data is displayed in a state of one dot short as shown in FIG. 20(a) or (b). Consequently, as shown in FIG. 19, the video data a to t cannot be simultaneously displayed.
Therefore, an object of the present invention is to provide a video signal processing device capable of, even with an A/D converter carrying out the two-phase processing, displaying every pixel on a display even if a head of video data is not in the first phase output data.
A first aspect of the present invention is directed to a video signal processing device for displaying, on a display, every pixel in a video signal inputted from an image signal source, the device comprising:
a clock delay circuit for receiving a reference signal, and delaying the reference signal by an odd number of clocks for output;
a multiplexer for selecting either the reference signal or an output signal from the clock delay circuit for output;
an A/D converter for converting the video signal into a digital signal for two-phase output as first phase data and second phase data with reference to an output signal from the multiplexer;
a first leading edge detection circuit for detecting a leading edge of a valid video signal region in the first phase data, and outputting a detection signal corresponding thereto;
a second leading edge detection circuit for detecting a leading edge of a valid video signal region in the second phase data, and outputting a detection signal corresponding thereto;
a first back porch detection circuit for detecting a first back porch period starting from the output signal from the multiplexer to the detection signal outputted from the first leading edge detection circuit;
a second back porch detection circuit for detecting a second back porch period starting from the output signal from the multiplexer to the detection signal outputted from the second leading edge detection circuit; and
a comparator for comparing the first back porch period and the second back porch period, and when the first back porch period is longer than the second back porch period, determining that head data in the valid video signal region in the video signal is not included in the first phase data, and outputting a signal for controlling the multiplexer to switch an output signal therefrom.
As described above, in the first aspect of the present invention, even if a head of video data is not included in first phase data under normal circumstances, a display can display every pixel by using a signal delayed by one clock phase.
According to a second aspect of the present invention, in the first aspect of the present invention,
the first back porch detection circuit detects the first back porch period by using the number of clocks in the video signal, and
the second back porch detection circuit detects the second back porch period by using the number of clocks in the video signal.
As described above, in the second aspect of the present invention, correct counting can be achieved by using the number of dot clocks coming from an image signal source.
According to a third aspect of the present invention, in the first aspect of the present invention, further comprising a first minimum value retention circuit for inputting, into the comparator, a minimum value of the first back porch periods outputted from the first back porch detection circuit as another first back porch period, and
a second minimum value retention circuit for inputting, into the comparator, a minimum value of the second back porch period outputted from the second back porch detection circuit as another second back porch period.
As described above, in the third aspect of the present invention, it is possible to deal with a case where a video signal from an image signal source is such a moving image that its back porch period does not stay the same. Therefore, a display can assuredly display every video signal.
A fourth aspect of the present invention is directed to a video signal processing device for displaying, on a display, every pixel in a video signal inputted from an image signal source, the device comprising:
a clock delay circuit for receiving a reference signal, and delaying the reference signal by an odd number of clocks for output;
a multiplexer for selecting either the reference signal or an output signal from the clock delay circuit for output;
an A/D converter for converting the video signal into a digital signal for two-phase output as first phase data and second phase data with reference to an output signal from the multiplexer;
a leading edge detection circuit for detecting, in a predetermined manner, a leading edge of a valid video signal region in either predetermined the first phase data or the second phase data, and outputting a detection signal corresponding thereto;
a back porch detection circuit for detecting a back porch period starting from the output signal from the multiplexer to the detection signal outputted from the leading edge detection circuit;
a storage part for receiving the back porch period, and storing and outputting in a manner each corresponding to the reference signal selected and outputted by the multiplexer and the output signal from the clock delay circuit; and
a comparator for outputting a control signal for controlling the multiplexer to switch a signal selected and outputted therefrom so that the storage part outputs a back porch period each corresponding to the signal selected and outputted from the multiplexer, comparing the corresponding back porch periods outputted from the storage part with each other, and when the back porch period corresponding to the reference signal is equal to or shorter than the back porch period corresponding to the output signal from the clock delay circuit, determining that head data in the valid video signal region in the video signal is included in the first phase data, and outputting the control signal again.
As described above, in the fourth aspect of the present invention, a display can assuredly display every video signal with such structure that a back porch period is stored and outputted in a manner corresponding to each state, and based on data outputted thereby, a comparator carries out its determination operation.
Also, in the fourth aspect of the present invention, a detection signal used therein is either first phase data or second phase data outputted from the A/D converter. Therefore, without using both data as the detection signal, the video signal processing device can be reduced in area for wiring on a substrate, for example.
According to a fifth aspect of the present invention, in the fourth aspect of the present invention, the back porch detection circuit detects the back porch period by using the number of clocks in the video signal.
As described above, in the fifth aspect of the present invention, correct counting can be achieved by using the number of dot clocks coming from an image signal source.
A sixth aspect of the present invention is directed to a video signal processing device for displaying, on a display, every pixel in a video signal inputted from an image signal source, the device comprising:
a clock delay circuit for receiving a reference signal, and delaying the reference signal by an odd number of clocks for output;
a multiplexer for selecting either the reference signal or an output signal from the clock delay circuit for output;
an A/D converter for converting the video signal into a digital signal for two-phase output as first phase data and second phase data with reference to an output signal from the multiplexer;
a leading edge detection circuit for detecting a leading edge of a valid video signal region in the first phase data, and outputting a detection signal corresponding thereto;
a falling edge detection circuit for detecting a falling edge of a valid video signal region in the second phase data, and outputting a detection signal corresponding thereto;
a valid video period detection circuit for detecting a valid video period starting from the detection signal outputted from the leading edge detection circuit to the detection signal outputted from the falling edge detection circuit; and
a comparator for comparing a value half of an inputted horizontal resolution with the valid video period, and when the value half of the horizontal resolution is larger than the valid video period in value, determining that head data in the valid video signal region in the video signal is not included in the first phase data, and outputting a signal for controlling the multiplexer to switch an output signal therefrom.
As described above, in the sixth aspect of the present invention, a display can assuredly display every video signal with such structure that a comparator receives the number of pixels detected by a valid video period detection circuit where receiving a detection pulse detected by each of a leading edge detection circuit and a falling edge detection circuit, and a value half of horizontal resolution from an image signal source connected to the present video signal processing device, and then carries out its determination operation.
According to a seventh aspect of the present invention, in the sixth aspect of the present invention, the valid video period detection circuit detects the valid video period by using the number of clocks in the video signal.
As described above, in the seventh aspect of the present invention, correct counting can be achieved by using the number of dot clocks coming from an image signal source.
An eighth aspect of the present invention is directed to a video signal processing device for displaying, on a display, every pixel in a video signal inputted from an image signal source, the device comprising:
a clock delay circuit for receiving a reference signal, and delaying the reference signal by an odd number of clocks for output;
a multiplexer for selecting either the reference signal or an output signal from the clock delay circuit for output;
an A/D converter for converting the video signal into a digital signal for two-phase output as first phase data and second phase data with reference to an output signal from the multiplexer;
a leading edge detection circuit for detecting a leading edge of a valid video signal region in the second phase data, and outputting a detection signal corresponding thereto;
a falling edge detection circuit for detecting a falling edge of the valid video signal region in the first phase data, and outputting a detection signal corresponding thereto;
a valid video period detection circuit for detecting a valid video period starting from the detection signal outputted from the leading edge detection circuit to the detection signal outputted from the falling edge detection circuit; and
a comparator for comparing a value half of an inputted horizontal resolution with the valid video period, and when the value half of the horizontal resolution is smaller than the valid video period in value, determining that head data in the valid video signal region in the, video signal is not included in the first phase data, and outputting a signal for controlling the multiplexer to switch an output signal therefrom.
As described above, in the eighth aspect of the present invention, no matter what the data included in a video signal is ON or OFF, a display can assuredly display every video signal with such structure that a comparator receives the number of pixels detected by a valid video period detection circuit where receiving a detection pulse detected by each of a leading edge detection circuit and a falling edge detection circuit, and a value half of horizontal resolution from an image signal source connected to the present video signal processing device, and then carries out its determination operation.
According to a ninth aspect of the present invention, in the eighth aspect of the present invention, the valid video period detection circuit detects the valid video period by using the number of clocks in the video signal.
As described above, in the ninth aspect of the present invention, correct counting can be achieved by using the number of dot clocks coming from an image signal source.
A tenth aspect of the present invention is directed to a video signal processing device for displaying, on a display, every pixel in a video signal inputted from an image signal source, the device comprising:
a clock delay circuit for receiving a reference signal, and delaying the reference signal by the odd number of clocks for output;
a multiplexer for selecting either the reference signal or an output signal from the clock delay circuit for output;
an A/D converter for converting the video signal into a digital signal for two-phase output as first phase data and second phase data with reference to an output signal from the multiplexer;
a first leading edge detection circuit for detecting a leading edge of a valid video signal region in the first phase data, and outputting a detection signal corresponding thereto;
a second leading edge detection circuit for detecting a leading edge of a valid video signal region in the second phase data, and outputting a detection signal corresponding thereto;
a first falling edge detection circuit for detecting a falling edge of the valid video signal region in the second phase data, and outputting a detection signal corresponding thereto;
a second falling edge detection signal for detecting a falling edge of the valid video signal region in the first phase data, and outputs a detection signal corresponding thereto;
a first valid video period detection circuit for detecting a first valid video period starting from the detection signal outputted from the first leading edge detection circuit to the detection signal outputted from the first falling edge detection circuit;
a second valid video period detection circuit for detecting a second valid video period starting from the detection signal outputted from the second leading edge detection circuit to the detection signal outputted from the second falling edge detection circuit; and
a comparator for comparing the first valid video period and the second valid video period, and when the second valid video period is longer than the first valid video period, determining that head data in the valid video signal region in the video signal is not included in the first phase data, and outputting a signal for controlling the multiplexer to switch an output signal therefrom.
As described above, in the tenth aspect of the present invention, a display can assuredly display every video signal with such structure that a valid video period is detected but not a horizontal resolution.
According to an eleventh aspect of the present invention, in the tenth aspect of the present invention,
the first valid video period detection circuit detects the first valid video period by using the number of clocks in the video signal, and
the second valid video period detection circuit detects the second valid video period by using the number of clocks in the video signal.
As described above, in the eleventh aspect of the present invention, correct counting can be achieved by using the number of dot clocks coming from an image signal source.
A twelfth aspect of the present invention is directed to a video signal processing device for displaying, on a display, every pixel in a video signal inputted from an image signal source, the device comprising:
an A/D converter for converting the video signal into a digital signal for two-phase output as first phase data and second phase data with reference to an incoming reference signal;
a clock delay circuit for receiving the second phase data, and delaying the second phase data by the odd number of clocks for output;
a first multiplexer for selecting either the first phase data or an output signal from the clock delay circuit for output;
a second multiplexer for selecting either the second phase data or the first phase data for output;
a first leading edge detection circuit for detecting a leading edge of a valid video signal region in the first phase data, and outputting a detection signal corresponding thereto;
a second leading edge detection circuit for detecting a leading edge of a valid video signal region in the second phase data, and outputting a detection signal corresponding thereto;
a first back porch detection circuit for detecting a first back porch period starting from the reference signal to the detection signal outputted from the first leading edge detection circuit;
a second back porch detection circuit for detecting a second back porch period starting from the reference signal to the detection signal outputted from the second leading edge detection circuit; and
a comparator for comparing the first back porch period and the second back porch period, and when the first back porch period is longer than the second back porch period, determining that head data in the valid video signal region in the video signal is not included in the first phase data, and outputting a signal for controlling the first and second multiplexers to switch an output signal each therefrom simultaneously, wherein
right after activation, the first multiplexer selects the first phase data for output, and the second multiplexer selects the second phase data for output.
As described above, in the twelfth aspect of the present invention, it is possible to deal with an image signal source having higher resolution, and thus a display can assuredly display every video signal.
According to a thirteenth aspect of the present invention, in the twelfth aspect of the present invention,
the first back porch detection circuit detects the first back porch period by using the number of clocks in the video signal, and
the second back porch detection circuit detects the second back porch period by using the number of clocks in the video signal.
As described above, in the thirteenth aspect of the present invention, correct counting can be achieved by using the number of dot clocks coming from an image signal source.